W6300 – TCP/IP Chip

Description

W6300 is a hardwired TCP/IP stack internet controller chip with WIZnet technology, designed for high-speed Ethernet communication. It integrates Dual IPv4/IPv6 hardware stack, 10/100 Ethernet MAC, and PHY in a single chip. To achieve performance over 90Mbps, W6300 supports a 150MHz system clock and QSPI interface with 4 data lines. It provides 8 independent SOCKETs and 64KB of internal SRAM, enabling reliable Ethernet application development through socket programming.

Features

• Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, IPv6, ARP, IGMP, PPPoE
• Supports 8 independent sockets simultaneously
• Supports Power down mode
• Supports Wake on LAN over UDP
• Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
• Internal 32Kbytes Memory for Tx/Rx Buffers
• 10BaseT/100BaseTX Ethernet PHY embedded
• Support Auto Negotiation (Full and half duplex, 10 and 100-based)
• Not support IP Fragmentation
• 3.3V operation with 5V I/O signal tolerance
• LED outputs (Full/Half duplex, Link, Speed, Active)
• 48 Pin LQFP Lead-Free Package (7x7mm, 0.5mm pitch)

Documents

• Datasheet
• Reference Schematic

Driver

• ioLibrary_Driver