W6100 – TCP/IP Chip

Description

 W6100 is a hardwired TCP/IP stack internet controller chip with WIZnet technology, supporting both IPv4 and IPv6. It integrates 10/100 Ethernet MAC and PHY and supports TCP, UDP, ICMPv4/v6, IGMP, ARP, and PPPoE protocols. W6100 provides 8 independent hardware SOCKETs and 32KB internal memory, making it easy to develop Ethernet applications using socket programming. It also supports WOL (Wake on LAN) and Power Down Mode for reduced power consumption, and offers SPI and Parallel System BUS interfaces.

Features

• Support Hardwired TCP/IP Protocols : TCP, UDP, IPv6, IPv4, ICMPv6, ICMPv4, IGMP, MLDv1, ARP, PPPoE
• Support IPv4/IPv6 Dual Stack
• Support 8 independent SOCKETs simultaneously with 32KB Memory
• Support SOCKET-less Command: ARP, PING, ICMPv6(PING, ARP,DAD,NA,RS) Command for IPv6 Auto-configuration& Network Monitoring
• Support Ethernet Power Down Mode & System Clock Switching for power save
• Support Wake on LAN over UDP
• Support Serial & Parallel Host Interface: High Speed SPI(MODE 0/3), System Bus with 2 Address signal & 8bit Data
• Internal 16Kbytes Memory for TX/ RX Buffers
• 10BaseT / 10BaseTe / 100BaseTX Ethernet PHY Integrated
• Support Auto Negotiation (Full and half duplex, 10 and 100-based )
• Support Auto-MDIX only on Auto-Negotiation Mode
• Not support IP Fragmentation
• 3V operation with 5V I/O signal tolerance
• Network Indicator LEDs (Full/Half Duplex, Link, 10/100 Speed, Active)
• 48 Pin LQFP & QFN Lead-Free Package (7x7mm, 0.5mm pitch)
• W5100S PIN-2-PIN Compatible

Documents

• Datasheet(KOR/ENG)
• Reference Schematic

Driver

• ioLibrary_Driver