W5500 – TCP/IP Chip

Description

W5500 is a Hardwired TCP/IP stack internet controller chip with WIZnet technology, which provides easy internet connectivity to an external MCU via an SPI interface of up to 80MHz. This chip is a one-chip solution with an embedded 10/100 Ethernet MAC and PHY, and it supports various protocols like TCP, UDP, and IPv4. Furthermore, it provides 8 independent SOCKETs and 32KB of internal memory, enabling the development of Ethernet applications simply by using the SOCKET program. It also reduces power consumption through WOL (Wake on LAN) and a Power Down Mode.

Features

• Supports following Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4, ARP, IGMP, PPPoE
• Supports 8 independent sockets simultaneously
• Supports Power down mode
• Supports Wake on LAN over UDP
• Supports High Speed Serial Peripheral Interface(SPI MODE 0, 3)
• Internal 32Kbytes Memory for Tx/Rx Buffers
• 10BaseT/100BaseTX Ethernet PHY embedded
• Support Auto Negotiation (Full and half duplex, 10 and 100-based)
• Not support Auto MDI/MDIX
• Not support IP Fragmentation
• 3.3V operation with 5V I/O signal tolerance
• LED outputs (Full/Half duplex, Link, Speed, Active)
• 48 Pin LQFP Lead-Free Package (7x7mm, 0.5mm pitch)

Documents

• Datasheet(KOR/ ENG)
• Reference Schematic(Transformer / RJ45)

Driver

• ioLibrary_Driver