W5100S – TCP/IP Chip

설명

W5100S is a hardwired TCP/IP stack internet controller chip with WIZnet technology, which provides easy internet connectivity to an external MCU via SPI or Parallel System BUS. The SPI interface supports up to 70MHz clock speed, while the Parallel System BUS provides higher data throughput for faster network communication. W5100S integrates an embedded Ethernet MAC and PHY, allowing developers to build Ethernet applications easily through socket programming.

Features

• Support Hardwired Internet Protocols: TCP, UDP, WOL over UDP, ICMP, IGMPv1/v2, IPv4, ARP, PPPoE
• Support 4 Independent Hardware SOCKETs simultaneously
• Support SOCKET-less Command: ARP-Request, PING-Request
• Support Ethernet Power Down Mode & Main Clock gating for power save
• Support Wake on LAN over UDP
• Support Serial & Parallel Host Interface: High Speed SPI(MODE 0/3), Parallel System Bus with 2 Address signal & 8bits Data
• Internal 16 Kbytes Memory for TX/ RX Buffers
• Not support IP Fragmentation
• Not Maintain ARP-cache Table
• 10BaseT/100BaseTX Ethernet PHY Integrated
• Support Auto Negotiation (Full/Half Duplex, 10/100 Speed)
• Support Auto-MDIX when Auto-Negotiation Mode.
• 3.3V operation with 5V I/O signal tolerance
• LED outputs (Full/Half Duplex, Link, 10/100 Speed, Active)
• Two types of packages: 48 Pin LQFP & QFN Lead-Free Package (7x7mm, 0.5mm pitch)

Documents

• Datasheet
• Errata
• Reference Schematic

Driver

• ioLibrary_Driver